1. Field of the Invention
The present invention relates to an ESD (Electrostatic Discharge) protection circuit of liquid crystal LVDS (Low-Voltage Differential Signaling) driving circuit, and in particular to a digitally displaying inspection system for ESD protection chip of liquid crystal LVDS driving circuit.
2. The Related Arts
Thin-film transistor liquid crystal display (TFT-LCD) is one of the main stream product for flat panel displaying and is a vital display platform for modern IT and video products.
Referring to FIG. 1, which is a schematic view illustrating the essential driving principle of TFT-LCD, the principle is that a system PCB (Printed Circuit Board) applies R/G/B compression signal, control signal, and driving signal to connect with LVDS connector of a PCB via wires and the PCB adopts an arrangement of directly coupling an LVDS data processing chip IC to source terminal and gate terminal of a flexible printed circuit board (Source-Chip on Film, S-COF, and Gate-Chip on Film, G-COF) to connect with a display zone so as to uses the gate terminal and source terminal to allow the LCD to obtain necessary power and signal.
The signals that a liquid crystal display system using such a way of driving a display zone transmits to the PCB main board are generally of an LVDS format. Signals of the LVDS format are of relatively low voltage and relatively high accuracy and are relatively sensitive to voltage variation so that any static electricity may cause damage on the LVDS data processing chip IC. However, it is generally impossible to avoid generating static electricity during a process of component insertion and removal. Thus, to avoid any damage of the LVDS data processing chip IC caused by static electricity generated during an insertion and removal operation with respect to the LVDS connector, it is a general practice to make an arrangement of an ESD protection circuit for important signals at the connection between the LVDS connector and the LVDS data processing chip IC.
As shown in FIG. 2, the ESD protection circuit is often comprised of an ESD protection chip 60. The ESD protection chip 60 comprises parallel connection of a voltage stabilizing diode and two serial-parallel structures that each comprise four diodes. For illustration of the effect of the ESD protection circuit, transmission of an LV1P0 signal from the LVDS connector 20 to the LVDS data processing chip IC 40 will be taken as an example. The LVDS connector 20 comprises an LV1P0 pin, an LV1N0 pin, an LV1P1 pin, and an LV1N1 pin, which are respectively connected to corresponding pins of the LVDS data processing chip IC 40, wherein the first pin LV1P0 is also connected to a branch of serial-parallel connection of the ESD protection chip 60. Similarly, the first opposite pin LV1N0 is also connected to another branch of serial-parallel connection of the ESD protection chip 60.
Under the assumption that the diodes constitute the ESD protection chip 60 are all of identical characteristics and forward conduction voltage drop is UD+, while reveres cutoff voltage drop is UD−, in an LVDS transmission circuit, with the voltage of a transmitted signal being U, UD+<U<UD− (wherein a normal LVDS signal is around 1.2 v; UD− is 3 v; and UD+ is 0.7 v). In a normal condition, when an normal LVDS signal is input through the LViP0 pin of the LVDS connector 20, since UD−>U, diode D0 of the ESD protection chip 60 is in a reverse cutoff condition. The voltage applied through the LV1P0 pin of the LVDS connector 20 cannot pass through the D0 to form a loop with the GND pin of the LVDS connector 20. Thus, the voltage applied to the LV1P0 pin of the LVDS connector 20 is identical to the LV1P0 pin of the LVDS data processing chip IC 40. The signal transmission route is that shown in the drawing and the signal can be normally transmitted to the LV1P0 pin of the LVDS data processing chip IC 40.
As shown in FIG. 3, when the ESD protection chip 60 is soldered to the PCB in a reversed manner, a normal LVDS signal input through the LV1P0 pin of the LVDS connector 20 will flow through diode D1 to the grounding line GND of the LVDS connector 20. Under this condition, the voltage of the LV1P0 pin of the LVDS data processing chip IC 40 is distorted and becomes the conduction voltage UD+ of diode D1, whereby the signal supplied to the display area of the display screen become abnormal, resulting in abnormality of image. Further, it is generally hard to identify front and back sides of the ESD protection chip so that it is difficult to visually distinguish an abnormally soldered product from normal products. This often results in shipping defect products to the client, causing damage of the client. Further, picking out abnormally soldered products takes a great effort and time and will cause an increase of manufacture cost.